Freescale Semiconductor /MK63F12 /I2S0 /TCR4

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Interpret as TCR4

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FSD 0 (0)FSP 0 (0)FSE 0 (0)MF 0SYWD0FRSZ

FSE=0, FSD=0, MF=0, FSP=0

Description

SAI Transmit Configuration 4 Register

Fields

FSD

Frame Sync Direction

0 (0): Frame sync is generated externally in Slave mode.

1 (1): Frame sync is generated internally in Master mode.

FSP

Frame Sync Polarity

0 (0): Frame sync is active high.

1 (1): Frame sync is active low.

FSE

Frame Sync Early

0 (0): Frame sync asserts with the first bit of the frame.

1 (1): Frame sync asserts one bit before the first bit of the frame.

MF

MSB First

0 (0): LSB is transmitted first.

1 (1): MSB is transmitted first.

SYWD

Sync Width

FRSZ

Frame size

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